ASICs for DSP

The problems of design and verification of a large digital ASIC have been discussed in many publications. Requirements for testability, power consumption, reliability and performance give the designer many issues to consider. Now, with a DSP system to implement, the designer has a whole range of additional problems: the choice of architecture, the word length required for coefficients and variables, quantisation effects such as limit cycles, spectral spurs, filter response distortion and possibly even the definition of novel DSP algorithms. Although many ASIC vendor libraries contain basic DSP components such as adders, multipliers, RAMs and ROMs, there are many questions to be answered by the designer before these components can be used to build the DSP system. High level simulation is essential to the DSP design process, in our experience the higher the better. Much can be done by simulating using languages such as C, but much more can be achieved using an integrated structure for modelling and simulation