DocumentCode :
1821467
Title :
Enhanced Schedulability Analysis of Hard Real-time Systems on Power Manageable Multi-core Platforms
Author :
He, Da ; Mueller, Wolfgang
Author_Institution :
C-Lab., Univ. of Paderborn, Paderborn, Germany
fYear :
2012
fDate :
25-27 June 2012
Firstpage :
1748
Lastpage :
1753
Abstract :
Nowadays, the multi-core platforms have become the de-facto solution to cope with the rapid increase of system complexity and energy consumption. Additionally, the dynamic power management (DPM) and the dynamic voltage and frequency scaling (DVS) are two well-established techniques to adjust the trade-off between the system performance and power consumption during runtime. However, in the context of hard real-time systems the DPM and DVS have to be applied with great caution due to timing constraints. The problem of DPM/DVS based power-aware scheduling has been extensively addressed on single-core platforms. Therefore some recent studies have proposed to adapt the existing results to multi-core platforms by performing the task partition in advance. In this article, we show that this approach may not work correctly any more, if the cluster-based multi-core platforms with non-negligible DPM and DVS state switching overhead are considered. More specifically, additional delays are introduced into the task execution and thus the traditional schedulability analysis becomes insufficient. We propose a simple runtime mechanism for idle time prediction to deal with the DPM state switching overhead and two solutions to enhance the schedulability analysis by taking the DVS state switching overhead into consideration: the conservative protocol and the speed inheritance protocol. Finally, the solutions are evaluated by means of simulation.
Keywords :
multiprocessing systems; power aware computing; processor scheduling; protocols; real-time systems; DPM-based power aware scheduling; DVS-based power aware scheduling; cluster-based multicore platforms; conservative protocol; de-facto solution; dynamic power manageable multicore platforms; dynamic voltage-and-frequency scaling; energy consumption; hard real-time systems; idle time prediction; nonnegligible DPM state switching overhead; nonnegligible DVS state switching overhead; runtime mechanism; schedulability analysis enhancement; speed inheritance protocol; system complexity; task execution; Delay; Iterative closest point algorithm; Multicore processing; Protocols; Real-time systems; Switches; Voltage control; Dynamic Power Management; Dynamic Voltage and Frequency Scaling; Hard Real-Time Systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on
Conference_Location :
Liverpool
Print_ISBN :
978-1-4673-2164-8
Type :
conf
DOI :
10.1109/HPCC.2012.263
Filename :
6332003
Link To Document :
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