Cluster-based test architecture design for system-on-chip

A test architecture for an SOC consists of a number of Test Access Mechanisms that connect to wrapped cores. This paper presents a new test architecture, named the TestRail Architecture, that is a hybrid form of the known Daisychain and Distribution Architectures. An important characteristic of the TestRail Architecture is that it allows for efficient testing of both the cores as well as the core-external circuitry. We present two alternative optimization algorithms for the TestRail Architecture, that minimize the total core-internal test time of the cores in the SOC. These algorithms handle both cores with fixed-length and flexible-length scan chains. Experimental results on three industrial benchmark SOCs show that, compared to previous publications, we obtain comparable or better test times at drastically reduced compute times.