Efficient code generation for in-house DSP-cores

A balance between efficiency and flexibility is obtained by developing a relative large number of in-house DSP-cores each for a relatively small application area. These cores are programmed using existing ASIC synthesis tools which are modified for this purpose. The key problem is to model conflicts arising from the instruction set. A class of instruction sets is defined for which conflicts can be modelled statically before scheduling. The approach is illustrated with a real life example