A Gauss-elimination based PRPG for combinational circuits

Author

Huang, Li-Ren ; Kuo, Sy-Yen ; Chen, Ing-Yi

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1995

fDate

6-9 Mar 1995

Firstpage

212

Lastpage

216

Abstract

A new algorithm for the reseeding of multiple polynomial LFSR for pseudorandom test pattern generation (PRPG) is proposed in this paper. It is based on the Gauss-elimination procedure and the deterministic test set generated by an ATPG software system for combinational circuits. In addition to the general LFSR model, we also provide two further improvements, ms1p and 1smp, to minimize the hardware overhead. Experimental results were obtained on ISCAS-85 benchmark circuits to demonstrate the effectiveness of this methodology. Complete fault coverage is achieved in all circuits. Low hardware overhead is also maintained with a reasonable test length

Keywords

automatic test software; combinational circuits; integrated circuit testing; integrated logic circuits; logic testing; 1smp; ATPG software system; Gauss-elimination based PRPG; algorithm; combinational circuits; deterministic test set; fault coverage; general LFSR model; low hardware overhead; ms1p; multiple polynomial LFSR; pseudorandom test pattern generation; reseeding; Automatic test pattern generation; Circuit testing; Combinational circuits; Gaussian processes; Hardware; Polynomials; Software systems; Software testing; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1995. ED&TC 1995, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-7039-8

Type

conf

DOI

10.1109/EDTC.1995.470390

Filename

470390