Sequential logic minimization based on functional testability

This paper presents a methodology for sequential logic minimization based on a functional testing approach. A new class of sequentially redundant faults, called functionally redundant, is defined. Such faults are determined by analyzing the functional description of a circuit; their identification and removal is the main topic of the paper. We show that by comparing the gate-level implementation of a circuit with its functional description, it is possible to produce fully testable circuits by spending a fraction of the time usually necessary for applying standard redundancies removal algorithms working at the gate level