A method of test generation for path delay faults in balanced sequential circuits

Author

Ohtake, Satoshi ; Miwa, Shunjiro ; Fujiwara, Hideo

Author_Institution

Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan

fYear

2002

fDate

2002

Firstpage

321

Lastpage

327

Abstract

This paper shows that path delay fault test generation problem for sequential circuits with balanced structure can be reduced to segment delay fault test generation problem for their combinationally transformed circuits. We also propose a test generation method and a partially enhanced scan design method for path delay fault.

Keywords

VLSI; delays; design for testability; digital integrated circuits; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; DFT; PDF testability; VLSI; balanced sequential circuits; combinationally transformed circuits; path delay fault test generation; scan design; segment delay; Circuit faults; Circuit testing; Delay; Design for testability; Feedback circuits; National electric code; Sequential analysis; Sequential circuits; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE

Print_ISBN

0-7695-1570-3

Type

conf

DOI

10.1109/VTS.2002.1011160

Filename

1011160

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1821694