Title :
Layout analysis to extract open nets caused by systematic failure mechanisms
Author :
Chakravarty, Sreejit ; Komeyli, Kambiz ; Savage, Eric W. ; Carruthers, Michael J. ; Stastny, Bret T. ; Zachariah, Sujit T.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Previously published work has pointed out that open defects are escaping test screens. To plug this hole, tests directed at nets susceptible to opens are required, and, therefore, nets susceptible to opens need to be identified. Opens caused by random particles have been modeled using weighted critical area (WCA) and have been previously studied. Here, we present a model that abstracts a class of systematic failure mechanisms that leads to open nets. An algorithm to calculate net scores using this model is presented. Experimental results on industrial designs show the algorithm to have reasonable performance.
Keywords :
VLSI; failure analysis; fault simulation; integrated circuit layout; integrated circuit modelling; integrated circuit testing; VLSI testing; algorithm; contact shelving; density gradient model; industrial designs; layout analysis; metal shelving; missing salicide defect; net scores; open defects; open nets extraction; systematic failure mechanisms; Abstracts; Algorithm design and analysis; Aluminum; Bridge circuits; Circuit faults; Circuit testing; Contacts; Copper; FETs; Failure analysis;
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
DOI :
10.1109/VTS.2002.1011166
