DocumentCode :
1822018
Title :
Improving initialization through reversed retiming
Author :
Stok, Leon ; Spillinger, Ilan ; Even, Guy
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
1995
fDate :
6-9 Mar 1995
Firstpage :
150
Lastpage :
154
Abstract :
Despite the fact that retiming circuits have a large potential (especially in automatically synthesized circuits from higher-level descriptions) it has not been widely included in the current design methodologies. One of the main problems is finding an equivalent initial state for the retimed logic. In this paper we introduce a new reverse retiming algorithm which will find a retiming for a given cycle time, if one exists. This new algorithm minimizes the effort required to find equivalent initial states and reduces the chance that the network needs to be modified to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings preserving the initial state condition
Keywords :
circuit optimisation; logic CAD; sequential circuits; timing; equivalent initial state; initialization; retimed logic; retiming circuits; reversed retiming algorithm; Circuit simulation; Circuit synthesis; Circuit testing; Delay; Design methodology; Kernel; Logic; Registers; Sequential circuits; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
Type :
conf
DOI :
10.1109/EDTC.1995.470405
Filename :
470405
Link To Document :
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