• DocumentCode
    1822023
  • Title

    Test economics for multi-site test with modern cost reduction techniques

  • Author

    Volkerink, Erik H. ; Khoche, Ajay ; Rivoir, Jochen ; Hilliges, Klaus D.

  • Author_Institution
    Agilent Labs., Palo Alto, CA, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    411
  • Lastpage
    416
  • Abstract
    Test approaches that can be combined with multisite, like reduced pin-count test, low channel cost ATE, and bandwidth matching, are becoming pervasive. Yet their economic benefits, the tradeoffs, and the long-term scalability of their benefits during technology progress, are not well understood In this paper the benefits and tradeoffs will be analyzed using technical cost modeling. The dependency of the benefits on the application are analyzed by modeling the test cost for 4 different applications. It is shown that the mentioned test approaches can result in a significant and scalable reduction of the Cost of Test.
  • Keywords
    automatic test equipment; integrated circuit economics; integrated circuit testing; microprocessor chips; IC testing; bandwidth matching; cost modeling; economics; low channel cost ATE; microprocessor testing; multisite; reduced pin-count test; scalability; Bandwidth; Circuit testing; Cost benefit analysis; Frequency; Integrated circuit technology; Laboratories; Pins; Scalability; System testing; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
  • Print_ISBN
    0-7695-1570-3
  • Type

    conf

  • DOI
    10.1109/VTS.2002.1011173
  • Filename
    1011173