DocumentCode
1822127
Title
Pseudo-exhaustive word-oriented DRAM testing
Author
Karpovsky, M.G. ; van de Goor, A.J. ; Yarmolik, V.N.
Author_Institution
Boston Univ., MA, USA
fYear
1995
fDate
6-9 Mar 1995
Firstpage
126
Lastpage
132
Abstract
This paper presents a new methodology for RAM testing based on the PS(n,k) q-ary fault model (q=2w) which includes most classical fault models for SRAMs and DRAMs. According to this fault model, the contents of any w-bit memory word of a memory with n words, or ability to change this contents, is influenced by the contents of any other k-1 words of the memory. The proposed methodology uses a pseudo-exhaustive technique based on Reed-Solomon codes, which can be efficiently applied to a word-oriented RAMs, assuming small values of k. The methodology ensures the detection of any number of disjoint (not linked) k-coupling faults, whereby the involved k words may be located anywhere in the memory; i.e., no assumptions have to be made on the physical topology of the cells in the memory cell array because of the systematic structure of the proposed tests, they are well suited for BIST implementations
Keywords
DRAM chips; Reed-Solomon codes; built-in self test; fault diagnosis; integrated circuit testing; BIST implementations; RS codes; Reed-Solomon codes; fault model; memory cell array; pseudo-exhaustive technique; word-oriented DRAM testing; Built-in self-test; Costs; Fault detection; Integrated circuit testing; Mathematical model; Random access memory; Read-write memory; Reed-Solomon codes; System testing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-7039-8
Type
conf
DOI
10.1109/EDTC.1995.470409
Filename
470409
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