• DocumentCode
    1823313
  • Title

    Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies

  • Author

    Li, Junjun ; Mishra, Rahul ; Shrivastava, Mayank ; Yang, Yang ; Gauthier, Robert ; Russ, Christian

  • Author_Institution
    Semicond. R&D Center, IBM, Essex Junction, VT, USA
  • fYear
    2011
  • fDate
    11-16 Sept. 2011
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    We present technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices. Stress elements and their effects are characterized using TLP and analyzed with the help of TCAD. Stress liners show no significant effect on ESD performance, whereas the source/drain eSiGe reduces on-resistance by up to 20% and failure current by up to 14%.
  • Keywords
    CMOS integrated circuits; MOSFET; electrostatic discharge; technology CAD (electronics); ESD performance; TCAD; failure current; nanometer bulk CMOS technologies; silicide-blocked PMOSFET devices; stress elements; technology scaling effects; CMOS integrated circuits; CMOS technology; Electrostatic discharge; Logic gates; MOSFET circuits; Performance evaluation; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
  • Conference_Location
    Anaheim, CA
  • ISSN
    Pending
  • Electronic_ISBN
    Pending
  • Type

    conf

  • Filename
    6045565
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1823313