DocumentCode :
1823454
Title :
ESD robust DeMOS devices in advanced CMOS technologies
Author :
Shrivastava, Mayank ; Russ, Christian ; Gossner, Harald ; Bychikhin, S. ; Pogany, D. ; Gornik, E.
Author_Institution :
Intel Mobile Commun., Essex Junction, VT, USA
fYear :
2011
fDate :
11-16 Sept. 2011
Firstpage :
1
Lastpage :
10
Abstract :
Improvement of ~5X in the IT2 (3.3mA/μm) of a grounded gate N-DeMOS device compared to a standard design is achieved by simple layout variations with a minor impact on its footprint. Robustness of P-DeMOS devices is shown to be further increased by additional p implant in drain region. Electrical and thermal instabilities are studied by Transmission Line Pulsing (TLP), Transient Interferometric Mapping (TIM) method and 3D TCAD simulations.
Keywords :
CMOS integrated circuits; MIS devices; electrostatic discharge; 3D TCAD simulation; ESD robust DeMOS device; P-DeMOS devices; TIM method; TLP; advanced CMOS technology; electrical instability; grounded gate N-DeMOS device; simple layout variation; thermal instability; transient interferometric mapping method; transmission line pulsing; Current density; Electric fields; Junctions; Logic gates; Solid modeling; Temperature measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location :
Anaheim, CA
ISSN :
Pending
Electronic_ISBN :
Pending
Type :
conf
Filename :
6045570
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1823454
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