Title :
Origin of It2 drop depending on process and layout with fully silicided ggMOS
Author :
Fukasaku, Katsuhiko ; Yamazaki, Takashi ; Kanno, Michihiro
Author_Institution :
Sony Corp., Atsugi, Japan
Abstract :
Source-drain process optimization and a diffusion layout technique enable reduction of the snapback voltage (Vt1). Lowering Vt1 of the fully silicided ggMOS enabled low on-resistance and a higher failure current (It2) combined stably in multi-finger turn-on operation. Moreover, to meet both hot-carrier reliability and the ESD requirement, lightly doped drain (LDD) process was obtained.
Keywords :
MOSFET; electrostatic discharge; hot carriers; semiconductor device reliability; semiconductor technology; ESD requirement; It2 drop; diffusion layout technique; failure current; fully silicided ggMOS; gate grounded MOS; hot carrier reliability; lightly doped drain process; low on-resistance; multifinger turn-on operation; snapback voltage reduction; source-drain process optimization; Electric fields; Electrostatic discharge; Hot carriers; Layout; Logic gates; Reliability; Silicides;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location :
Anaheim, CA
Electronic_ISBN :
Pending
