DocumentCode
1823749
Title
Process variation aware ESD design window considerations on a 0.18μm analog, mixed-signal high voltage technology
Author
Roger, Frederic ; Reinprecht, Wolfgang ; Minixhofer, Rainer
Author_Institution
Austriamicrosystems, Schloss Premstatten, Austria
fYear
2011
fDate
11-16 Sept. 2011
Firstpage
1
Lastpage
7
Abstract
The boundary conditions leading to the “ESD Design Window” like the trigger diode characteristics, process variability, parameters drift because of low temperature, and voltage drop of the ESD circuit elements (forward diode, central clamp, bus resistance) are investigated and put into context. A 0.18μm High Voltage Technology is analyzed with respect to these constraints.
Keywords
electrostatic discharge; mixed analogue-digital integrated circuits; power integrated circuits; ESD circuit elements; analog signal high voltage technology; bus resistance; central clamp; forward diode; mixed-signal high voltage technology; process variability; process variation aware ESD design window; size 0.18 mum; trigger diode characteristics; voltage drop; Clamps; Doping; Electrostatic discharge; Junctions; Resistance; Semiconductor diodes;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location
Anaheim, CA
ISSN
Pending
Electronic_ISBN
Pending
Type
conf
Filename
6045580
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