Title :
A predictive full chip dynamic ESD simulation and analysis tool for analog and mixed-signal ICs
Author :
Tian, Guangchun ; Xiao, Yunpeng ; Connerney, Duane ; Kang, Taeghyun ; Young, Alister ; Liu, Qiang
Author_Institution :
Fairchild Semicond. Technol. (Shanghai), Shanghai, China
Abstract :
We present a successfully implemented dynamic ESD simulation, verification and analysis tool, DynEsdChecker, that can simulate the ESD event on the layout containing RC extractions, can generate full chip ESD verification results, can provide user with guidelines on how to revise the design to meet the ESD design target.
Keywords :
analogue integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit modelling; mixed analogue-digital integrated circuits; DynEsdChecker; ESD design target; ESD verification; RC extractions; analog IC; analysis tool; mixed signal IC; predictive full chip dynamic ESD simulation; Breakdown voltage; Electrostatic discharge; Hardware design languages; Integrated circuit modeling; MOSFETs; Simulation;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location :
Anaheim, CA
Electronic_ISBN :
Pending
