A comparison of defect models for fault location with Iddq measurements

Author

Aitken, Robert C.

Author_Institution

Hewlett-Packard Co., Santa Clara, CA, USA

fYear

1993

fDate

17-21 Oct 1993

Firstpage

1051

Lastpage

1060

Abstract

Iddq testing, where quiescent current is measured for a variety of states in static CMOS circuits, has emerged as a useful fault detection technique. In this paper it is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models. The effects of these models are compared, using chips from a standard cell ASIC run. Of the 151 parts in the sample, diagnoses have been obtained from 135 of them. In many of these cases, the predicted defects are confined to a single standard cell

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; electric current measurement; failure analysis; fault diagnosis; fault location; integrated circuit reliability; integrated circuit testing; logic testing; semiconductor device models; short-circuit currents; diagnosis; fault detection; fault location; fault models; inter-gate shorts; intra-gate shorts; quiescent current; single standard cell; standard cell ASIC; static CMOS circuits; Circuit faults; Circuit testing; Current measurement; Electrical fault detection; Fault diagnosis; Fault location; Predictive models; Semiconductor device modeling; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1993. Proceedings., International

Conference_Location

Baltimore, MD

Print_ISBN

0-7803-1430-1

Type

conf

DOI

10.1109/TEST.1993.470593

Filename

470593