Design of scan-based path delay testable sequential circuits

Several techniques that produce robust path delay testable designs for arbitrary combinational logic functions have been recently proposed. Unfortunately, these often results in circuits with longer delays. Moreover, such designs also assume extra hardware in the form of "holding" latches in the scan-chain in order to apply arbitrary vector-pairs, as required for high coverage delay testing. This results in high area overheads. In this paper, we present a scan-based design for testability technique for arbitrary sequential circuits. This new scheme allows a delay vs. area tradeoff while enforcing delay fault testability. At one end of the spectrum, a fully robust path delay testable circuit is guaranteed with very low additional hardware overheads in the form of extra latches. At the other end, full robust path delay testability is ensured without compromising the overall circuit delay, and with hardware overheads