DocumentCode
1825493
Title
High speed sampling capability for a VLSI mixed signal tester
Author
Sakamoto, Paul ; Chiu, Tom
Author_Institution
Megatest Corp., San Jose, CA, USA
fYear
1993
fDate
17-21 Oct 1993
Firstpage
918
Lastpage
927
Abstract
This article describes the design of a high bandwidth sampled data measurement system and its integration with a high pin-count, high speed digital component tester. The unique "time-list" architecture of this design enhances testing throughput and measurement flexibility. In addition, the innovation hardware design allows measurement of signal jitter with 10 ps of resolution
Keywords
VLSI; automatic test equipment; automatic testing; computer architecture; integrated circuit testing; mixed analogue-digital integrated circuits; sampled data systems; VLSI mixed signal; high bandwidth sampled data measurement; high speed digital component tester; high speed sampling; measurement flexibility; signal jitter; time list architecture; Bandwidth; Hardware; Jitter; Sampling methods; Signal design; System testing; Technological innovation; Throughput; Velocity measurement; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1993. Proceedings., International
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-1430-1
Type
conf
DOI
10.1109/TEST.1993.470608
Filename
470608
Link To Document