Title :
Testable programmable digital clock pulse control elements
Author :
Wagner, Kenneth D. ; Koenemann, Bernd K.
Author_Institution :
Synopsys, Inc., Mountain View, CA, USA
Abstract :
Digital clock pulse control elements - delay lines and pulse-shaping elements - are used widely for clock generation and clock tuning in synchronous digital logic. However, they are intrinsically redundant circuits: without special modifications, DC logic testing cannot completely verify their static behavior (including the correct operation of the decoders and selectors used for their programming and control). This paper demonstrates low overhead circuit modification techniques that can be applied to all classes of programmable clock control elements, ensuring their complete single stuck-at fault testability
Keywords :
clocks; delays; design for testability; logic testing; pulse shaping circuits; redundancy; sampled data circuits; tuning; DC logic testing; clock generation; clock tuning; decoders; delay lines; intrinsically redundant circuits; overhead circuit modification; programmable digital clock pulse control; pulse-shaping elements; selectors; single stuck-at fault testability; static behavior; synchronous digital logic; Circuit optimization; Circuit testing; Clocks; Decoding; Delay lines; Digital control; Logic programming; Logic testing; Pulse generation; Synchronous generators;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470610
