5.5GHz LSNA MOSFET modeling for RF CMOS circuit design

Author

Grabinski, W. ; Vandamme, E.P. ; Schreurs, D. ; Maeder, H. ; Pilloud, O. ; McAndrew, C.C.

Author_Institution

Geneva Modeling Lab., Motorola, Le Grand Saconnex, Switzerland

fYear

2002

fDate

5-6 Dec. 2002

Firstpage

39

Lastpage

47

Abstract

The recent trend towards integrating an entire transceiver, with all its RF/analog/DSP functions, on a single CMOS chip is a consequence of strong market demands on RF chip size, cost, reliability, battery-life, etc. The design of a modern RF CMOS chips generates various technical challenges due to circuit complexity, signal complexity, and integration issues. Advanced LSNA characterization and modeling of deep submicron devices are critical to modern RF CMOS circuit design. This paper reviews some of the RF device level modeling technologies required for the design of RFICs. The LSNA modeling is performed using Agilent´s characterization, parameter extraction and simulation tools flow.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit design; network analysers; semiconductor device models; 5.5 GHz; DSP function; LSNA MOSFET modeling; RF CMOS circuit design; RF chip size; RF function; analog function; circuit complexity; complementary metal oxide semiconductor; deep submicron device; digital signal processing; large signal network analyzer; metal oxide semiconductor field effect transistor; parameter extraction; signal complexity; Circuit synthesis; Cost function; Digital signal processing chips; Integrated circuit reliability; MOSFET circuits; Radio frequency; Semiconductor device modeling; Signal design; Signal generators; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

ARFTG Conference Digest, Fall 2002. 60th

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-8124-6

Type

conf

DOI

10.1109/ARFTGF.2002.1218684

Filename

1218684