Title :
Cu wire bonding for fine pitch 40nm circuit under pad silicon integrated circuits: Development of a comprehensive robust Cu wire bonding process
Author :
Wang, Bq ; Emerich, Sue ; Davison, Kerry ; Rossi, Nick ; Osenbach, John
Author_Institution :
LSI Corp. China, Shanghai, China
Abstract :
Historically Cu wire has been targeted to lower pin count high power discrete devices and consumer product for a long time. As gold costs increased the industry started focusing on moving more mainstream products to Cu wire. Markets that have seen the largest growth in Cu wire bonded products include consumer electronics, communication devices and industrial electronics etc. However, Cu wire has been used sparingly in high reliability markets which require stringent and extensive reliability performance. One of the reasons is that the leading edge silicon nodes with low-k/ELK device bonding pads are vulnerable to damage during wire bond process even with gold wire. In this manuscript our work on the development of a comprehensive protocol, experimental procedure and exhaustive characterization of a highly reliable Cu wire bonding process and bill of materials for use on wire bond devices made in leading edge silicon node technologies is summarized. Included in the work was the application of this development process to multiple aspects of the overall process and materials selection including but not limited to: i) Cu wire bond process development at five different manufacturing locations owned by three different assembly suppliers; ii) three different mold compounds; iii) three different package types; and iv) multiple integrated circuit designs, all with circuit under pad. Also summarized are the extensive reliability evaluations that were completed through the course of this work. Using these exhaustive protocols, experimental procedures, characterizations and reliability studies, we successfully developed a robust bond pad design, which in combination with the wire bond process and bill of materials results in highly reliable Cu wire bonded devices in advanced silicon technology nodes.
Keywords :
copper; elemental semiconductors; integrated circuit bonding; integrated circuit packaging; integrated circuit reliability; silicon; Cu; Cu wire bonding; Si; low-k/ELK device bonding pads; multiple integrated circuit design; package type; reliability evaluation; robust bond pad design; silicon integrated circuit; size 40 nm; Assembly; Bonding; Compounds; Copper; Gold; Reliability; Wires;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
Conference_Location :
Singapore
Print_ISBN :
978-1-4577-1983-7
Electronic_ISBN :
978-1-4577-1981-3
DOI :
10.1109/EPTC.2011.6184376