Design for testability of a modular, mixed signal family of VLSI devices

Recent advances in semiconductor design and fabrication have made it possible to integrate an entire system including digital microcontrollers, memories, analog and power devices onto a single silicon chip. The complexity of test has increased greatly due to the embedded nature of these devices and also the significant economic pressure to maximize the number of analog/power pins and minimize test access pins. This paper describes the application of previously developed DFT techniques to a configurable family of highly integrated mixed signal devices and the strategy for achieving modular re-usable tests for mixed signal automatic test equipment