Title :
Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging
Author :
Buisson, T. ; Potoms, G. ; Phommahaxay, A. ; Verbinnen, G. ; Jaenen, P. ; Manna, A. La ; Travaly, Y. ; Beyne, E.
Author_Institution :
IMEC vzw, Heverlee, Belgium
Abstract :
In this paper, we report on the development of Cu pillars and their impact on the subsequent thinning process for 3D applications. As the Cu pillars have a height of tens of microns (typically between 50-100μm), controlling the total thickness variation (TTV) after wafer thinning is becoming even more challenging. The Cu pillars are processed after completion of the Back End of Line (BEOL) with a target thickness of 50μm for a diameter of 80μm and a pitch of 200μm. The key challenge for 3D integration is the control of the wafer TTV after back grinding in order to allow TSV reveal. After optimization of the temporary wafer bonding in presence of high topography induced by 50μm high Cu pillars, a TTV after thinning below 5μm is achieved, which is comparable to the TTV obtained after wafer thinning without topography.
Keywords :
copper; elemental semiconductors; three-dimensional integrated circuits; wafer bonding; wafer level packaging; 3D integration; 3D packaging; 3D stacking; BEOL; Cu; TSV reveal; back end of line; back grinding; copper pillars; extreme wafer thinning; size 50 mum; size 80 mum; target thickness; temporary wafer bonding; thinning process; total thickness variation; wafer TTV; Bonding; Coatings; Copper; Resists; Silicon; Surfaces; Three dimensional displays;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
Conference_Location :
Singapore
Print_ISBN :
978-1-4577-1983-7
Electronic_ISBN :
978-1-4577-1981-3
DOI :
10.1109/EPTC.2011.6184379