DocumentCode :
1826076
Title :
A conditional resource sharing method for behavioral synthesis of highly testable data paths
Author :
Lee, Tien-Chien ; Jha, Niraj K. ; Wolf, Wayne H.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fYear :
1993
fDate :
17-21 Oct 1993
Firstpage :
744
Lastpage :
753
Abstract :
Existing conditional resource sharing methods using in behavioral synthesis focus on area and performance optimization and do not consider testability. This paper extends our previous work to handle conditional branches. A hierarchical control-data flow graph (HCDFG) is used to model the system behavior. A postorder traversal of the HCDFG is employed to reduce sequential depths and loops for testability synthesis. Experimental results for the benchmarks show that our method, with no a priori test strategy assumption, can achieve higher fault coverage in shorter test generation time than an algorithm which disregards testability, and, with partial scan test assumption, can have high testability with fewer scan registers than some design-for-test methods
Keywords :
computational complexity; design for testability; fault diagnosis; logic CAD; logic design; logic testing; optimisation; behavioral synthesis; conditional branches; conditional resource sharing; design-for-test; hierarchical control-data flow graph; loops; partial scan test; performance optimization; postorder traversal; sequential depths; testability synthesis; testable data paths; Automatic testing; Benchmark testing; Circuit synthesis; Circuit testing; Control system synthesis; Design for testability; Flow graphs; Optimization; Resource management; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
Type :
conf
DOI :
10.1109/TEST.1993.470628
Filename :
470628
Link To Document :
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