Title :
High Performance Memory Requests Scheduling Technique for Multicore Processors
Author :
El-Reedy, Walid ; El-Moursy, Ali A. ; Fahmy, Hossam A H
Author_Institution :
Electron. & Comm. Eng., Cairo Univ., Cairo, Egypt
Abstract :
In modern computer systems, long memory latency is one of the main bottlenecks micro-architects are facing for leveraging the system performance especially for memory-intensive applications. This emphasises the importance of the memory access scheduling to efficiently utilize memory bandwidth. Moreover, in recent micro-processors, multithread and multicore is turned to be the default choice for their design. This resulted in more contention on memory. Hence, the effect of memory access scheduling schemes is more critical to the overall performance boost. Although memory access scheduling techniques have been recently proposed for performance improvement, most of them have overlooked the fairness among the running applications. Achieving both high-throughput and fairness simultaneously is challenging. In this paper, we focus on the basic idea of memory requests scheduling, which includes how to assign priorities to threads, what request should be served first, and how to achieve fairness among the running applications for multicore microprocessors. We propose two new memory access scheduling techniques FLRMR, and FIQMR. Compared to recently proposed techniques, on average, FLRMR achieves 8.64% speedup relative to LREQ algorithm, and FIQMR achieves 11.34% speedup relative to IQ-based algorithm. FLRMR outperforms the best of the other techniques by 8.1% in 8-cores workloads. Moreover, FLRMR improves fairness over LREQ by 77.2% on average.
Keywords :
coprocessors; multi-threading; multiprocessing systems; processor scheduling; storage management; FIQMR; FLRMR; high performance memory requests scheduling; memory access scheduling; memory bandwidth; memory intensive application; memory latency; microarchitect; multicore microprocessor; multithread processor; priority assignment; throughput; Benchmark testing; Instruction sets; Multicore processing; Scheduling; Scheduling algorithms; Throughput; Computer architecture; Memory management; Multicore processing;
Conference_Titel :
High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on
Conference_Location :
Liverpool
Print_ISBN :
978-1-4673-2164-8
DOI :
10.1109/HPCC.2012.26