A method to derive compact test sets for path delay faults in combinational circuits

In path delay fault testing, the number of faults to be tested in a circuit is inherently very large. Therefore, deriving compact test sets for path delay faults is an important issue. This paper presents a method to derive compact test sets for path delay faults by using the notion of compatible faults. A technique to derive maximal compatible path delay fault sets is described. The technique is based on identifying necessary conditions on lines in a circuit along with values a line cannot take in order to test a given path. Experimental results on ISCAS benchmarks are presented to demonstrate the effectiveness of using this technique in reducing test set size