Combined unsigned and two´s complement squarers

Squaring is an important operation in digital signal processing applications. For several applications, a significant reduction in area, delay, and power consumption is achieved by performing squaring using specialized squarers, instead of multipliers. Although most previous research on parallel squarers focuses on the design of unsigned squarers, squaring of two´s complement numbers is also often required. This paper presents the design of parallel squarers that perform either unsigned or two´s complement squaring, based on an input control signal. Compared to unsigned parallel squarers, these squarers require only a small amount of additional delay and area.