DocumentCode
1826235
Title
Interconnection effects in fast multipliers
Author
Choe, Gwangwoo ; Swartzlander, Earl E., Jr.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
2
fYear
1999
fDate
24-27 Oct. 1999
Firstpage
1224
Abstract
Interconnections strongly influence the speed of VLSI fast multipliers as devices are scaled down in deep submicron geometry. Relatively high interconnection resistance makes fast multipliers less favorable for simple uniform scaling technique. Fast multipliers with various word lengths have been evaluated for speeds by running a sub-micron interconnect simulation.
Keywords
MOS integrated circuits; VLSI; electric resistance; integrated circuit interconnections; multiplying circuits; MOS devices; VLSI fast multipliers; deep submicron geometry; fast multiplication algorithm; high interconnection resistance; interconnection effects; metal oxide semiconductor devices; multiplier speed; sub-micron interconnect simulation; uniform scaling technique; word lengths; Adders; Computational geometry; Delay; Electric resistance; Integrated circuit interconnections; Matrix converters; Routing; Space technology; Transmission line matrix methods; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-5700-0
Type
conf
DOI
10.1109/ACSSC.1999.831902
Filename
831902
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