Simulation, fabrication and characterization of Dual-Gate MOSFET test structures

Ion-Sensitive Field-Effect Transistor (ISFET) is a popular potentiometric chemical/bio-chemical sensor. However, due to charge screening, the sensitivity of the device is significantly reduced. A logarithmic dependence is exhibited between the charge present at the electrolyte-insulator interface and the charge mirrored in the conducting channel, which limits the sensitivity of an ideal conventional ISFET to 59.2 mV/pH, also known as the Nernstian limit. Using Dual-Gate effect in Silicon-on-Insulator (SOI) technology improves the sensitivity of ISFET. MOSFET test structures are generally fabricated along with ISFETs on the same wafer. In this paper, we have demonstrated the dual gate operation of a Near-Fully Depleted (NFD) SOI MOSFET, by simulating its behavior in SILVACO™ TCAD tool and validating it with the test results of fabricated NFDSOI MOSFET. It is observed that the threshold voltage and drain current of the transistor can be manipulated by applying a potential to the back gate.