• DocumentCode
    1826291
  • Title

    A simple component connection approach for fault tree conversion to binary decision diagram

  • Author

    Remenyte, R. ; Andrews, J.D.

  • Author_Institution
    Dept. of Aeronaut. & Automotive Eng., Loughborough Univ., UK
  • fYear
    2006
  • fDate
    20-22 April 2006
  • Abstract
    Fault tree analysis (FTA) is commonly used when conducting risk assessments of industrial systems. A number of computer packages based on conventional analysis methods are available to perform the analysis. However, dealing with large (possibly non-coherent) fault trees can expose the limitations of the technique in terms of accuracy of the solutions and the processing time required. Over recent years the binary decision diagram (BDD) method has been developed for the solution of the fault tree and overcomes the disadvantages of the conventional FTA approaches. The usual way of taking advantage of the BDD structure is to construct a fault tree and then convert it to a BDD. This paper focuses on the fault tree to BDD conversion process. Converting the fault tree requires the basic events of the fault tree to be placed in an ordering. This is critical to the size of the final BDD and ultimately affects the qualitative and quantitative analysis of the system and benefits of this method. Once the ordering is established several approaches can be used for the BDD generation. One approach is to apply a set of rules developed by Rauzy which are repeatedly applied to each gate in the fault tree to generate the BDD. An alternative approach can be used when BDD constructs for each of the gate types are first built and then connected together. A sub-node sharing feature in the second of these approaches and a third, hybrid, combined approach is presented. Some remarks on the effectiveness of these techniques are provided.
  • Keywords
    binary decision diagrams; fault trees; logic gates; BDD conversion process; binary decision diagram; component connection approach; fault tree conversion; logic gates; risk assessments; Automotive engineering; Binary decision diagrams; Boolean functions; Data structures; Fault trees; Logic functions; Performance analysis; Risk analysis; Risk management; US Department of Transportation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Availability, Reliability and Security, 2006. ARES 2006. The First International Conference on
  • Print_ISBN
    0-7695-2567-9
  • Type

    conf

  • DOI
    10.1109/ARES.2006.17
  • Filename
    1625342