Test pattern generation with restrictors

This paper extends state-of-the-art ATPG systems by including constraints, called restrictors, on the allowable values of the bits of a test vector. Such restrictors often occur in "real-world" circuits where certain bit positions of a test vector have to take on a particular value (e.g. in case of a reset line) or are prohibited from taking on a particular value (e.g. in order to prevent an illegal state to be entered). This paper describes the types of restrictors, as encountered in "real world" circuits; it shows the required modifications to ATPG algorithms for stuck-at faults in combinational circuits, in order to cope with restrictors; and finally, the results of experiments determining the consequences for the ATPG time and fault coverage are given. The overall conclusion is: restrictors can easily be implemented in any ATPG system; the use of restrictors is essential in "real-world" circuits; the influence of restrictors on the ATPG time is small while a new class of "redundant faults" is identified, belonging to that part of the circuit which cannot be tested due to the specified restrictors