PowerPC processors

Author

Marsala, Anthony ; Kanawati, Basel

fYear

1994

fDate

20-22 Mar 1994

Firstpage

550

Lastpage

556

Abstract

In October of 1991, IBM, Apple, and Motorola formed an alliance to produce a new microprocessor family named the PowerPC. Less than two years later, the alliance has produced the first chip of the PowerPC family, the MPC601. The paper analyzes the PowerPC 6xx family, with an emphasis on the architecture of the MPC6O1 chip. The 601´s Reduced Instruction Set Computer (RISC) architecture is examined, including the three parallel execution units (integer unit, branch unit, and floating point unit), the instruction unit, the memory management unit, and the system interface. In addition, the software environments for the PowerPC are discussed. Finally, conclusions about the chip are drawn and an outlook on the future of the PowerPC family is made

Keywords

computer interfaces; instruction sets; microprocessor chips; parallel architectures; reduced instruction set computing; storage management; MPC601; PowerPC 6xx family; PowerPC processors; RISC; Reduced Instruction Set Computer; architecture; branch unit; floating point unit; instruction unit; integer unit; memory management unit; microprocessor family; parallel execution units; software environments; system interface; CMOS process; Clocks; Computer aided instruction; Computer architecture; Computer interfaces; Concurrent computing; Costs; Memory management; Microprocessors; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory, 1994., Proceedings of the 26th Southeastern Symposium on

Conference_Location

Athens, OH

ISSN

0094-2898

Print_ISBN

0-8186-5320-5

Type

conf

DOI

10.1109/SSST.1994.287816

Filename

287816