Implementation of a 1.5V low-power clock-jitter insensitive continuous-time ΣΔ modulator

Author

Gerfers, F. ; Ortmanns, M. ; Samid, L. ; Mano, Y.

Author_Institution

Inst. of Microelectron., Saarlandes Univ., Saarbrucken, Germany

Volume

2

fYear

2002

fDate

2002

Abstract

The design of a low-power clock-jitter insensitive continuous-time ΣΔ modulator is presented. The circuit uses a time-variant feedback digital-to-analog converter (DAC) to reduce the clock jitter influence. Special care was taken to the overall power consumption of the modulator. In order to show the power efficiency of this technique in comparison to the standard non-retum-to-zero DAC, behavioral simulations considering finite DC-gain, GBW and slew-rate were done. Additional it will be shown that the proposed concept is suitable for very low supply voltages. The modulator operates at a 1.5V power supply and achieves a signal-to-noise+distortion-ratio (SNDR) of 70dB for a 25kHz signal bandwidth. The test chip was realized in a 3.3V, 0.5-μm CMOS DPTM process.

Keywords

CMOS integrated circuits; circuit feedback; continuous time systems; digital-analogue conversion; low-power electronics; sigma-delta modulation; timing jitter; 0.5 micron; 1.5 V; 25 kHz; CMOS DPTM process; DC gain; SNDR; behavioral simulation; clock jitter; gain-bandwidth product; low-power continuous-time ΣΔ modulator; power consumption; power efficiency; slew rate; time-variant feedback digital-to-analog converter; Bandwidth; Circuit simulation; Clocks; Digital-analog conversion; Energy consumption; Feedback circuits; Jitter; Low voltage; Power supplies; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1011437

Filename

1011437