Express Router Microarchitecture for Triplet-based Hierarchical Interconnection Network

Network-on-Chip (NoC) Router has an important impact on the network communication performance. High performance router will help to build a high-throughput, power-efficient and low-latency NoC. However, the existing baseline router of Triplet-based Hierarchical Interconnection Network (THIN) can not fully exert the potential performance of THIN because it does not consider the characteristic of THIN topology. This paper proposes a topology-related express router microarchitecture for THIN, named E-THIN. Four measures are taken to optimize the baseline router microarchitecture including simplified crossbar switch, express virtual channel for THIN, group-priority scheme and shared buffer organization. Simulation results using a cycle-accurate simulator Noxim show the E-THIN reduces up to 55% packet latency, improves up to 12% throughput, and reduces 8% energy consumption per packet over a baseline router microarchitecture.