DocumentCode
1826579
Title
A new implementation of the discrete cosine transform in the residue number system
Author
Fernández, P.G. ; Garcia, A. ; Ramírez, J. ; Parrilla, L. ; Lloris, A.
Author_Institution
Dept. of Electr. Eng., Jaen Univ., Spain
Volume
2
fYear
1999
fDate
24-27 Oct. 1999
Firstpage
1302
Abstract
A field-programmable logic (FPL) implementation of a discrete cosine transform (DCT) based on the residue number system (RNS) is presented. Compared with a binary distributed arithmetic implementation, the presented architecture provides approximately 21% throughput improvement. Moreover, the performance improvement over a conventional binary implementation is up to 103%. This is achieved due to the synergy between RNS and modern FPL device families.
Keywords
discrete cosine transforms; programmable logic arrays; residue number systems; DCT implementation; discrete cosine transform; field-programmable logic implementation; performance improvement; residue number system; throughput improvement; Arithmetic; Computer architecture; Digital signal processing; Discrete cosine transforms; Discrete transforms; Dynamic range; Image coding; Logic devices; Pipeline processing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-5700-0
Type
conf
DOI
10.1109/ACSSC.1999.831917
Filename
831917
Link To Document