Title :
A novel RNS-based SIMD RISC processor for digital signal processing
Author :
Ramírez, J. ; García, A. ; Parrilla, L. ; Fernández, P.G. ; Lloris, A.
Author_Institution :
Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain
Abstract :
The architectural design and field-programmable logic (FPL) implementation of a digital signal processor (DSP) based on the residue number system (RNS) is presented. This processor makes use of the intrinsic parallelism of RNS for high speed digital signal processing. It consists of a certain number of RNS channels that perform data processing in parallel without any dependency between them. In this way, efficiency is achieved by the reduction in channel word-length. The processor has been modelled at the structural level using VHDL and implemented in Altera FLEX10K devices. Comparison with commercial DSPs for several applications reveals an improvement of up to 133%.
Keywords :
digital signal processing chips; field programmable gate arrays; hardware description languages; integrated circuit modelling; parallel architectures; reduced instruction set computing; residue number systems; 32 bit; 8 bit; ASIC VLSI; Altera FLEX10K devices; DSP; RNS channels; RNS-based SIMD RISC processor; VHDL; architectural design; channel word-length reduction; commercial DSP; digital signal processing; digital signal processor; field-programmable logic implementation; high speed digital signal processing; parallel data processing; residue number system; Acceleration; Adders; Arithmetic; Bandwidth; Data processing; Digital signal processing; Parallel processing; Propagation delay; Reduced instruction set computing; Signal processing algorithms;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.831918
