DocumentCode :
1826752
Title :
Efficient designs for multi-input counters
Author :
Yeh, Chi-Hsiang ; Parhami, Behrooz
Author_Institution :
Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont., Canada
Volume :
2
fYear :
1999
fDate :
24-27 Oct. 1999
Firstpage :
1340
Abstract :
A multi-input counter, or accumulative parallel counter, represents a true generalization of a sequential counter in that it incorporates the memory feature of an ordinary counter; i.e., it adds the sum of its inputs to a stored value. In this paper, we present efficient designs for simple multi-input counters and their modular versions, which keep the accumulated count module an arbitrary constant.
Keywords :
counting circuits; logic design; parallel processing; pipeline arithmetic; accumulated count module; accumulative parallel counter; efficient design; memory; modular counters; multi-input counters; pipeline counter; sequential counter; serial circuit; Application software; Circuit testing; Computer applications; Concurrent computing; Counting circuits; Delay; Digital systems; Hardware; Instruments; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
ISSN :
1058-6393
Print_ISBN :
0-7803-5700-0
Type :
conf
DOI :
10.1109/ACSSC.1999.831925
Filename :
831925
Link To Document :
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