Title :
PSBIST: A partial-scan based built-in self-test scheme
Author :
Lin, Chih-Jen ; Zorian, Yervant ; Bhawmik, Sudipta
Author_Institution :
AT&T Bell Lab., Princeton, NJ, USA
Abstract :
Partial-scan based built-in self-test (PSBIST) is a versatile design for testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. While PSBIST provides all the benefits of BIST, it incurs less area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage
Keywords :
boundary scan testing; built-in self test; design for testability; integrated circuit testing; logic testing; random processes; IC; area overhead; boundary scan cells; built-in self-test; design for testability; deterministic partial scan; fault coverages; pseudo-random BIST; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Degradation; Design for testability; Flip-flops; Integrated circuit testing; Stress; Very large scale integration;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470660
