Architectures for adaptive weight calculation on ASIC and FPGA

Author

Walke, R.L. ; Smith, R W M ; Lightbody, G.

Author_Institution

DERA, Malvern, UK

Volume

2

fYear

1999

fDate

24-27 Oct. 1999

Firstpage

1375

Abstract

We compare two parallel array architectures for adaptive weight calculation based an QR-decomposition by Givens rotations. We present FPGA implementations of both architectures and compare them with an ASIC-based solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost are not critical.

Keywords

adaptive signal processing; application specific integrated circuits; array signal processing; digital arithmetic; field programmable gate arrays; parallel architectures; 5 to 20 GFLOPS; ASIC; CORDIC; FPGA; Givens rotations; QR-decomposition; adaptive beamforming; adaptive weight calculation; antenna arrays; parallel array architectures; power consumption; radar system; throughput; volume cost; Adaptive arrays; Application specific integrated circuits; Arithmetic; Array signal processing; Costs; Energy consumption; Field programmable gate arrays; Laboratories; Radar antennas; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-5700-0

Type

conf

DOI

10.1109/ACSSC.1999.831931

Filename

831931