Title :
A low-power, reconfigurable adaptive equalizer architecture
Author :
Tschanz, Jim ; Shanbhag, Naresh R.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents an architecture for an adaptive equalizer that is dynamically reconfigurable for low-power operation. The equalizer is composed of a signal processing block which accomplishes the filtering operations and a signal monitoring block which controls reconfiguration by monitoring the equalizer performance and dynamically powering up or down filter taps in order to conserve energy. This reconfigurable equalizer is used in the design of a 51.84 Mb/s VDSL receiver core, and simulation results are shown which demonstrate the power savings accomplished through reconfiguration.
Keywords :
CMOS digital integrated circuits; adaptive equalisers; digital signal processing chips; digital subscriber lines; receivers; reconfigurable architectures; 0.35 mum; 51.84 Mbit/s; CMOS process; VDSL receiver core; energy conservation; equalizer performance; filter taps; filtering operations; low-power adaptive equalizer architecture; power savings; reconfigurable adaptive equalizer architecture; signal monitoring block; signal processing block; simulation results; Adaptive equalizers; Algorithm design and analysis; Circuits; Energy consumption; Heuristic algorithms; Optical fiber cables; Optical fiber networks; Optical network units; Signal processing; Signal processing algorithms;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.831934
