Low cost fcCSP based on cu pillar

Flip chip (fc) packaging has been practiced for many years but mainly for high end computer and certain automotive devices. RoHS has driven the conversion from lead-based fc bumps to lead-free (Pb-free) bumps. Pb-free was adopted more readily in consumer and mobile applications than in high reliability applications. A few years back, Intel introduced copper pillars (CuP) as an alternative to high Pb bumps to minimize electro-migration which was found at high currents in high performance applications. CuP was used in conjunction with Pb-free solder thereby achieving compliance with RoHS while at the same time improving reliability with superior electro-migration and thermal performance. Now, mobile applications are adopting CuP but primarily for fine pitch applications. CuPs are invariant in height and diameter during reflow unlike solder bumps which were also termed controlled chip collapse connections (C4). C4s have the advantage of self-aligning during solder reflow i.e. placement accuracy does not have to be extremely precise. With the advent of high precision die bonders, die with CuPs and small solder caps can be placed sufficiently accurate to enable mass reflow connections. CuPs do enable other significant advantages which do enable significant cost reductions. The fixed diameter of the pillars provides a larger pillar to pillar spacing as compared solder bumps at the same pitch and stand-off. The larger spacing which avoids any shorting concerns also potentially allows additional traces between bumps/pillars, thereby increasing the routability. Or alternatively, wider traces/spaces can be employed in the substrate design which equates to simpler substrate processes albeit lower substrate costs. The higher stand-off facilitates mold-only underfill processing which is also a significant process simplification i.e. cost reduction. Of course CuPs also present new challenges due to the very high stiffness, especially when assembled to lowK or ELK dies. Finite El- ment Modeling (FEM) has provided successful guidelines to overcome the stress induced damage that had been observed initially. Here, the advantages of CuP based fcCSP packaging will be detailed with design rules for pillars and substrates to achieve cost reductions. Further, FEM results and design guides for die CuP bumping will be given and substantiated by stress test results. Finally, a roadmap for CuP-fcCSP will be presented.