Title :
1.1-GDI/s transmission between pausible clock domains
Author :
De Clercq, Mark ; Negulescu, Radu
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
Asynchronous across-chip communication is increasingly attractive as clock distribution is becoming increasingly difficult at smaller feature sizes. Several globally asynchronous locally synchronous architectures (GALS), proposed recently, use handshaking protocols for across-chip communication. In this paper, we design two circuits that interface synchronous modules using pausible clocks to an asynchronous communication environment that uses single-track handshaking, a protocol shown to support high-speed asynchronous logic. The resulting circuits allow data transfer rates of up to 1.1 GigaDataItems/second, significantly higher than previous designs
Keywords :
CMOS logic circuits; asynchronous sequential logic; clocks; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; protocols; 0.18 μm CMOS process; 0.18 micron; 1.1 Giga data items per second; asynchronous across-chip communication; asynchronous communication environment; clock distribution; data transfer rates; globally asynchronous locally synchronous architectures; handshaking protocols; heterogeneous pausible clock domains; high-speed asynchronous logic; single-track adaptor operation; single-track handshaking; synchronous module interfaces; Asynchronous communication; Circuits; Clocks; Data communication; Energy consumption; Logic; Metastasis; Protocols; Synchronous generators; Terminology;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1011466
