A 6.4 Gbps FIFO design for 8-32 two-way data exchange bus

Author

Wang, Chua-Chin ; Hsueh, Ya-Hsin ; Chen, E- Wei

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

2

fYear

2002

fDate

2002

Abstract

An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened. Two pointers, which are read pointer (RP) and write pointer (WP), respectively, point to the head and the tail of the valid data queue in the FIFO. The simulation results of the proposed design which is implemented by Verilog HDL (hardware description language) reveal that the design is capable of processing the data under a 200 MHz clock rate without pads using TSMC 0.35 μm 1P4M CMOS technology.

Keywords

CMOS memory circuits; circuit CAD; circuit simulation; electronic data interchange; hardware description languages; integrated circuit layout; memory architecture; system buses; 0.35 micron; 200 MHz clock rate; 6.4 Gbit/s; 8-32 two-way data exchange bus; FIFO memory architecture; TSMC 0.35 μm 1P4M CMOS technology; Verilog HDL; chip layout; input sequences; multi-processor systems; nonhomogeneous bus widths; output sequences; processing unit data exchange; read pointer; simulation results; write pointer; CMOS process; CMOS technology; Clocks; Codecs; Delay; Hardware design languages; Logic design; Memory architecture; Resilience; Tail;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1011467

Filename

1011467