A new time-interleaved architecture for high-speed A/D converters

Time-interleaved ADCs (TIADCs) are among the fastest architectures adopted when speed is the bottleneck of the system. Real-time medical imaging and networked video are few examples of many applications using such fast ADCs. The spurious-free dynamic range (SFDR) is an important parameter of high-speed TIADCs. We propose a new time-interleaved ADC architecture that reduces the spurious components and allow us to obtain better SFDR with reasonable addition of control and delay circuits to the ADC. The proposed architecture is digitally oriented, i.e. does not need complex analog circuitries. Matlab simulations show the effectiveness of the proposed approach in a multichannel ADC with arbitrary bit resolution and sampling rate. For a 12 bit ADC, the SFDR achieved using the proposed randomizing method can be as wide as -78 dBc.