Title :
A test methodology for VLSI chips on silicon
Author_Institution :
IBM Corp., Manassas, VA, USA
Abstract :
This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer level, unpopulated substrate, and populated substrate, is then detailed
Keywords :
CMOS integrated circuits; VLSI; elemental semiconductors; integrated circuit testing; packaging; silicon; Si; VLSI CMOS ICs; multichip silicon substrate; package technology; populated substrate; test strategy; unpopulated substrate; CMOS process; CMOS technology; Costs; Packaging; Power capacitors; Silicon; Space technology; Substrates; Testing; Very large scale integration;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470677
