Structure and metrology for an analog testability bus

Author

Parker, Kenneth P. ; McDermid, John E. ; Oresjo, Stig

Author_Institution

Hewlett-Packard Co., Loveland, CO, USA

fYear

1993

fDate

17-21 Oct 1993

Firstpage

309

Lastpage

317

Abstract

This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4. The proposed testability structure is imposed on the I/O pin cells of the analog and mixed technology ICs. It is a superset of the existing IEEE/ANSI 1149.1 testability standard for digital ICs and is intended to cooperate with it. This allows for the testing of interconnect failures such as shorts and opens, the testing of discrete analog components and networks between ICs, and supports the testing of analog functions within the ICs themselves. This paper is a companion to the result of a cooperative effort between AT&T, Ford Motor, Hewlett-Packard, Motorola and the University of Colorado at Colorado Springs

Keywords

IEEE standards; analogue integrated circuits; automatic test equipment; automatic testing; integrated circuit testing; mixed analogue-digital integrated circuits; system buses; AT&T; Ford Motor; Hewlett-Packard; IEEE P1149.4.; IEEE/ANSI 1149.1 testability standard; Motorola; University of Colorado; analog IC; analog functions; analog testability bus; discrete analog components; interconnect failures; metrology; mixed technology ICs; opens; shorts; testability structure; Analog integrated circuits; Circuit testing; Digital integrated circuits; Integrated circuit interconnections; Manufacturing; Metrology; Pins; Software standards; Software testing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1993. Proceedings., International

Conference_Location

Baltimore, MD

Print_ISBN

0-7803-1430-1

Type

conf

DOI

10.1109/TEST.1993.470682

Filename

470682