Title :
A comparison of stuck-at fault coverage and IDDQ testing on defect levels
Author :
Wiscombe, Paul C.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
This paper presents experimental data comparing the effect of functional stuck-at fault testing and IDDQ testing on defect levels. Results obtained for parts tested with varying stuck-at fault coverage are compared with results from IDDQ testing. Empirical data are analyzed against two theoretical fault models to demonstrate that correlation can be obtained. The results indicate that significant benefits can be gained from IDDQ testing, even with non-deterministic test locations and relatively few measurements. Data are also presented on the impact of IDDQ testing on burn-in monitoring and customer field failures of ASIC designs. Finally some practical issues associated with implementing IDDQ tests are discussed
Keywords :
VLSI; application specific integrated circuits; automatic test equipment; electric current measurement; fault location; integrated circuit modelling; integrated circuit testing; integrated logic circuits; ASIC designs; IDDQ testing; burn-in monitoring; defect levels; functional testing; nondeterministic test location; stuck-at fault coverage; theoretical fault models; Application specific integrated circuits; Circuit faults; Circuit testing; Condition monitoring; Data analysis; Fault detection; Gain measurement; Software testing; Timing; Very large scale integration;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470684
