DocumentCode
1827528
Title
Redistribution layer (RDL) process development and improvement for 3D interposer
Author
Li, H.Y. ; Chua, H.M. ; Che, F.X. ; Trigg, Alastair David ; Teo, K.H. ; Gao, S.
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2011
fDate
7-9 Dec. 2011
Firstpage
341
Lastpage
344
Abstract
RDL process becomes more and more important with through Si interposer (TSI) application in 3D packaging. RDL line/space needs to be shrinking with the increasing of device density. We had been developed low temperature (LT) damascene process for the RDL formation in 3D interposer integration. The sample failed at thermal reliability test. High temperature (HT) RDL was developed and demonstrated after TSV annealing temperature optimization in this paper.
Keywords
elemental semiconductors; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; silicon; three-dimensional integrated circuits; Si; TSV annealing temperature optimization; interposer 3D packaging; low temperature damascene process; redistribution layer process development; thermal reliability test; Annealing; Copper; Dielectrics; Reliability; Silicon compounds; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
Conference_Location
Singapore
Print_ISBN
978-1-4577-1983-7
Electronic_ISBN
978-1-4577-1981-3
Type
conf
DOI
10.1109/EPTC.2011.6184442
Filename
6184442
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