Title :
Reversed nested Miller compensation with voltage follower
Author :
Cataldo, G. Di ; Mita, R. ; Palumbo, G. ; Pennisi, S.
Author_Institution :
Dipt. Elettrico Elettronico e Sistemistico, Catania Univ., Italy
Abstract :
In this contribution we present a very efficient design approach for the frequency compensation of three-stage amplifiers using the reversed nested Miller technique. The method exploits a single voltage follower into the internal loop to remove the positive zero, avoiding the reduction of the output swing. Low-valued compensation capacitors are also required, improving speed and reducing area occupation
Keywords :
CMOS analogue integrated circuits; SPICE; compensation; integrated circuit design; integrated circuit modelling; operational amplifiers; CMOS three-stage amplifiers; SPICE simulations; area occupation reduction; design approach; differential stages; frequency compensation; internal loop; inverting stage; level 3 model parameters; low-valued compensation capacitors; output swing reduction; positive zero removal; reversed nested Miller compensation; speed improvement; unity-gain configuration; voltage follower; Application specific integrated circuits; Bandwidth; Capacitance; Capacitors; Circuit topology; Communication switching; Frequency; Operational amplifiers; Switching circuits; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1011481
